The objective of this experiment is to design a passive, 1st order, low pass filter with a break frequency of 100 Hz. Following proper lab procedure the circuit will first be designed theoretically by developing the transfer function and using mathematical equations to arrive at a solution. The design will then be tested using both Excel and MultiSIM to verify the theoretical solution. Once the design is verified using MultiSIM and Excel, the physical construction of the circuit will be performed using National Instruments NI ELVIS and an analysis of its operation will be verified and recorded.
Capacitive low pass filters work because the reactance of the capacitor is high at low frequencies and blocks any current flow through the capacitor effectively passing it all out the output. All frequencies that are below the designed cut off (break frequency) of 100Hz are passed with very little attenuation. The break frequency of 100Hz is the frequency at which the capacitive reactance and resistance become equal. At this point the output signal is attenuated to .707 volts of the one volt input (70.7 percent of any input). As the frequency continues to increase there is a roll off of -20dB/decade. The signals above 100Hz become greatly attenuated, until the reactance of the capacitor becomes so low that it acts like a short, resulting in zero output. Since the circuit contains a capacitor, the phase angle lags and at the frequency break (100Hz) it is out of phase by -45 degrees. This phase shift is caused by the time it takes the capacitor to charge and the higher the frequency the more it lags and becomes out of phase.
The design of the 1st order, low pass filter with a break frequency of 100Hz will be done using mathematics. First a value for capacitance will be decided. Once the value for capacitance is decided and the value for break frequency is known, the value for resistance can be solved. In a 1st order low pass filter only two components are needed, theoretically speaking. Since it is a low pass filter, the resister is placed in the circuit first making it and the capacitor voltage in (Vin). The capacitor is placed second, making it voltage out (Vout). Refer to diagram one.